1. Field of the Invention
The present invention relates to a semiconductor integrated circuit wiring design method, and a semiconductor integrated circuit.
2. Background Art
Recently, in the field of the semiconductor integrated circuit wiring design, it has been a common practice to create redundancy in the layout patterns after the designing of wiring is completed in order to secure a certain level of wiring density, taking into consideration the controllability of processing accuracy in the manufacture process, as described in, e.g., Japanese Patent Laid-Open Publication No. 312738/1999.
FIGS. 18–20 are layout patterns for explaining an example of such a conventional semiconductor integrated circuit wiring method.
FIG. 19 shows a layout pattern of an upper layer (first metal layer), and FIG. 20 shows a layout pattern of a lower layer (second metal layer). That is to say, the wiring layer includes the two layers, i.e., the upper and the lower layers, and the wiring traces 1a, 1a, . . . formed on the upper layer as shown in FIG. 19 are connected to the wiring traces 2a, 2a, . . . formed on the lower layer as shown in FIG. 20 through vias (not shown), thereby forming the wiring pattern shown in FIG. 18, i.e., completing the wiring of the device. In FIG. 19, the wiring traces 1a, 1a . . . , which serve as preferential wiring traces, extend in the horizontal direction in the drawing. In FIG. 20, the wiring traces 2a, 2a . . . , which serve as preferential wiring traces, extend in the vertical direction in the drawing. In FIGS. 19 and 20, the traces other than the wiring traces are redundant traces 1b, 1b, . . . , 2b, 2b . . . . 
That is to say, as shown in these drawings, the wiring in the semiconductor integrated circuit is formed by using the stacked layers, i.e., the first metal layer 1 and the second metal layer 2.
As described above, the conventional semiconductor integrated circuit wiring method includes determining, in each wiring layer, a direction in which preferential traces extend, setting a wiring grid so that the wiring can be formed in accordance with a predetermined design standard, and forming desired wiring traces in a free space, based on the aforementioned conditions and standard. However, as the miniaturization process has advanced, a problem of process accuracy has arisen. Since it has become difficult to form only the layout pattern that is necessary to form the signal wiring (including the wiring traces 1a and 2a), an increase in density of layout traces in the upper and the lower wiring layers is required. For this purpose, conventionally, redundant traces 1b and 2b are formed in the free space that is not occupied by the wiring traces 1a and 2a to adjust the trace density. That is to say, redundancy is made after the wiring design is finished. This method has various problems. For example, conventionally, the redundant traces 1b and 2b are formed at the time of the generation of mask data after the wiring design is completed in order to improve the metal coverage rate in each wiring layer and to increase the density in traces. This may cause a problem, however, in that because the positions to put redundant traces are decided after the wiring design is completed, there is a possibility that short-circuit verification for redundant traces is omitted. Furthermore, since the redundant traces are put at random in the area to which no wiring traces are provided, there is a possibility that the actual processing steps are difficult. Under such circumstances, there is a demand that the redundant layout traces formed to increase the pattern density in each wiring layer have regularity and uniformity.
Besides the metal layers (wiring patterns), via layers (serving as relay wiring layers) for connecting the metal wiring lines are also requested to increase the pattern density in view of the improvement in controllability of processing accuracy. That is to say, in the field of semiconductor integrated circuits, which will be more and more miniaturized, there is a strong demand for a wiring method that can improve the processing accuracy and controllability.
As described above, conventionally, redundant traces are formed at the time of the generation of mask data after the formation of wiring pattern. Because of this, the verification of redundant traces cannot be sufficiently performed. Furthermore, since the redundant traces are formed later, it is difficult for the redundant traces to have satisfactory regularity, which may cause a problem of processing accuracy and controllability.